TVHSAC 2010 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

In IC designs today, analog content is no longer a small portion of silicon as it was in the past. With various interfaces such as PCIe, DDR, Display-IO, HT, and other components such as PLLs, DACs, Temperature Sensors, the proportion of silicon die area covered by analog circuits is continually increasing with each design generation. Starting with 65nm process technology, a growing market need for high speeds, large bandwidths and small geometries have made designs a lot more complex in terms of testability and manufacturability. Majority of test for analog portions of a chip have been marginalized to characterization on the ATE and boards. This characterization is often planned around various electrical and thermal corners and the outcome is heavily dependent on process technology. More often than not, rigorous testing of the full range of properties of an analog circuit is neglected during production-ramp and production. Prime among the many reasons for this lack of rigor in test of analog circuits is overall test cost.

Key Dates

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Workshop Begins November 4th!

The Venue

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The ITC conference and all associated Test Week events will be held at the Austin Convention Center, Austin, Texas. Austin is the capital of the state of Texas, and its 1888 capitol building is an interesting landmark. Also of interest are the main campus of The University of Texas and the Lyndon B. Johnson Library and Museum. Close to the convention center is the lively East Sixth Street entertainment district which features many restaurants and a variety of music in the ―Live Music Capital of the World‖. The downtown area has miles of waterfront trails suitable for walking and jogging and is also home to the largest urban bat population in the US whose spectacular flight can be observed just before sunset. For more information about Austin, visit http://www.austintexas.org. Lodging for Test Week is in several hotels in the vicinity of the convention center.

Workshop Registration

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Register Onsite Now!

Advance Program

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Thursday -- Friday

November 4, 2010 (Thursday)

4:00 PM - 5:15 PM	Session 1 - Opening and Keynote Address
4:00 - 4:15	Welcome Address General Chairs: Andre Ivanov – UBC, Canada Abhijit Chatterjee – Georgia Tech., USA Program Chairs: Sassan Tabatabaei – SiTime, Canada Haralampos-G. Stratigopoulos – TIMA Laboratory/CNRS, France
4:15 - 5:15	Keynote: 20 years of Gigahertz Test Development - Timing is Everything David Keezer – Georgia Tech., USA

5:15 PM - 5:45 PM	Session 2 - Invited Address
5:15 - 5:45	Low Cost Testing for mmWave Devices: A Case Study Yiorgos Makris – Yale University, USA

7:00 PM - 9:00 PM WORKSHOP RECEPTION

November 5, 2010 (Friday)

7:00 AM - 8:00 AM WORKSHOP BREAKFAST

8:00 AM - 9:00 AM	Session 3 - BIST and Self-Calibration
8:00 - 8:30	All Digital Self-Calibration Technique for Feedback Systems Ping-Ying Wang – MediaTek Inc., Taiwan
8:30 - 9:00	A BIST Circuit that Tests Multiple Analog Functions Simultaneously Stephen Sunter – Mentor Graphics, Canada

9:00 AM - 9:30 AM	Session 4 - Invited Address
9:00 - 9:30	Automated Match Circuits and System Control Techniques for RF Testing and Verification William R. Eisenstadt – University of Florida, USA

9:30 AM - 10:00 AM	Session 5 - Invited Address
9:30 - 10:00	Beyond the Science Project: Pushing the Envelope on ATE Larry Luce – Teradyne, USA

10:30 AM - 12:00 PM	Session 6 - Test Generation
10:30 - 11:00	Leveraging a Standard Register Set and Integrated Development Environment to Optimize Test and Validation of Mixed-Signal SerDes blocks in SOCs Araon Burgmeier – Freescale Semiconductor, USA Junwei Chau – Freescale Semiconductor, USA Thecla Chomicz – Freescale Semiconductor, USA
11:00 - 11:30	The Dangers of Analogue IP ATPG Models in a Digital World Gary Morton – STMicroelectronics, UK
11:30 - 12:00	Kawela EV-like Test in Production Yossi Tal – Intel, Israel

12:00 PM - 1:00 PM WORKSHOP LUNCHEON

1:00 PM - 2:00 PM	Session 7 - PLL Testing
1:00 - 1:30	An All-Digital BIST Technique for Transfer Function Characterization of RF PLLs Hsiu-Ming (Sherman) Chang – UCSB, USA Ping-Ying Wang – National Taiwan University and MediaTek Inc., Taiwan Kwang-Ting (Tim) Cheng – UCSB, USA
1:30 - 2:00	A Bit-Stream Approach to PLL Testing Sadok Aouini – McGill University, Canada Kun Chuai – McGill University, Canada Gordon W. Roberts – McGill University, Canada

2:20 PM - 4:00 PM	Session 8 - Panel Discussion Challenges and Solutions in High-Speed Analog IC Testing
	Panelists: Stephen Sunter – Mentor Graphics, Canada Ping-Ying Wang – MediaTek Inc., Taiwan Larry Luce – Teradyne, USA

4:00 PM WORKSHOP CLOSURE

More Information

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General Information

Andre Ivanov
Tel: +1-604-822-2342
Fax: +1-604.822.5949
E-mail: ivanov@ece.ubc.ca

Committees

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General Chairs
Andre Ivanov, UBC
Abhijit Chatterjee, Georgia Tech.

Vice General Chair
Yervant Zorian, Synopsys

Program Chair
Sassan Tabatabaei, SiTime
Haralampos Stratigopoulos, TIMA

Publicity
Yiorgos Makris, Yale Univ.

Finance
Chen-Huan Chiang, Alcatel-Lucent

Publication
Dimitris Gizopoulos, Uni. Piraeus

Program Committee
Kwang-Ting (Tim) Cheng, UCSB
Prashant Goteti, Intel
Christophe Kelma, NXP
Hervé LeGall, STMicroelectronics
Anne Meixner, Intel
Tatevik Melkumyan, Synopsys
Jochen Rivoir, Verigy
Gordon Roberts, McGill Univ.
Arani Sinha, AMD
Steve Sunter, Mentor Graphics
Suriyaprakash Natarajan, Intel
Alberto Valdes-Garcia, IBM

For more information, visit us on the web at: http://entity.eng.yale.edu/trela/tvhsac10/

The 2nd IEEE International Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC 2010 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).